1 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com edi8f32256c aug. 2001 rev. 13 eco #14561 256kx32 static ram cmos, high speed module the edi8f32256c is a high speed 8mb static ram module organized as 256k words by 32 bits. this module is constructed from eight 256kx4 static rams in soj packages on an epoxy laminate (fr4) board. four chip enables (e?-e3) are used to independently enable the four bytes. reading or writing can be executed on individual bytes or any combination of multiple bytes through proper use of selects. the edi8f32256c is offered in 64 pin zip/simm package which enables eight megabits of memory to be placed in less than 1.4 square inches of board space. all inputs and outputs are ttl compatible and operate from a single 5v supply. fully asynchronous circuitry requires no clocks or refreshing for operation and provides equal access and cycle times for ease of use. the zip and simm modules contain two pins, pd1 and pd2, which are used to identify module memory density in applications where alternate modules can be interchanged. features ? 256kx32 bit cmos static ? random access memory ? access times: 12, 15, 20, and 25ns ? individual byte selects ? fully static, no clocks ? ttl compatible i/o ? high density package with jedec standard pinouts ? 64 pin zip, no. 85 ? 64 lead angled simm, no. 32 ? 64 lead simm, no. 333 ? common data inputs and outputs ? single +5v (10%) supply operation pin names pin configurations and block diagram a?-a17 address inputs e?-e3 chip enables w, write enables g output enable dq?-dq31 common data input/output vcc power (+5v10%) vss ground fig. 1 description
2 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com edi8f32256c aug. 2001 rev. 13 eco #14561 absolute maximum ratings* recommended dc operating conditions dc electrical characteristics capacitance (f=1.0mhz, vin=vcc or vss) ac test conditions (note: for tehqz,tghqz and twlqz, cl = 5pf) *typical: ta = 25c, vcc = 5.0v truth table these parameters are sampled, not 100% tested. *stress greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. voltage on any pin relative to vss -0.5v to 7.0v operating temperature ta (ambient) commercial 0c to +70c industrial -40c to +85c storage temperature, plastic -55c to +125c power dissipation 8.0 watt output current 20 ma input pulse levels vss to 3.0v input rise and fall times 5ns input and output timing levels 1.5v output load 1ttl, cl = 30pf parameter sym min typ max units supply voltage vcc 4.5 5.0 5.5 v supply voltage vss 0 0 0 v input high voltage vih 2.2 -- vcc+0.3v v input low voltage vil -0.3 -- 0.8 v parameter sym conditions min max units 12-25 ns operating power supply current icc1 w, e = vil, ii/o = 0ma, min cycle 800 ma standby (ttl) power supply current icc2 e 3 vih, vin vil or vin 3 vih 240 ma full standby power supply current icc3 e 3 vcc-0.2v 40 ma cmos vin 3 vcc-0.2v or vin 0.2v input leakage current ili vin = 0v to vcc -- 80 a output leakage current ilo v i/o = 0v to vcc -- 20 a output high voltage voh ioh = -4.0ma 2.4 ? v output low voltage vol iol = 8.0ma ? 0.4 v e w g mode output power h x x standby high z icc3 l h l read dout icc1 l l x write din icc1 l h h output deselect high z icc1 parameter sym max unit address lines ci 60 pf data lines cd/q 20 pf chip enable line cc 20 pf write control line cn 60 pf
3 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com edi8f32256c aug. 2001 rev. 13 eco #14561 ac characteristics read cycle read cycle 2 - w high note 1: parameter guaranteed, but not tested. read cycle 1 - w high, g, e low fig. 3 fig. 2 symbol 12ns 15ns 20ns 25ns parameter jedec alt. min max min max min max min max units read cycle time t avav trc 12 15 20 25 ns address access time tavqv taa 12 15 20 25 ns chip enable access telqv tacs 12 15 20 25 ns chip enable to output in low z (1) telqx tclz 3 3 3 3 ns chip disable to output in high z (1) tehqz tchz 6 7 9 9 ns output hold from address change tavqx toh 3 3 3 3 ns output enable to output valid tglqv toe 6 7 9 9 ns output enable to output in low z (1) tglqx tolz 0 0 0 0 ns output disable to output in high z (1) tghqz tohz 6 7 9 9 ns address 1 address 2 tavav data 1 data 2 tavqv tavqx a q tghqz telqv telqx e g q tehqz a tavav tglqv tglqx tavqv
4 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com edi8f32256c aug. 2001 rev. 13 eco #14561 note 1: parameter guaranteed, but not tested. ac characteristics write cycle symbol 10ns 12ns 15ns 20ns 25ns parameter jedec alt. min max min max min max min max min max units write cycle time t avav twc 10 12 15 20 25 ns chip enable to end of write telwh tcw 7 8 12 10 10 ns twleh tcw 7 8 10 10 10 ns address setup time tavwl tas 0 0 0 0 0 ns tavel tas 0 0 0 0 0 ns address valid to end of write tavwh taw 7 8 10 10 10 ns taveh taw 7 8 10 10 10 ns write pulse width twlwh twp 7 8 10 10 10 ns teleh twp 7 8 10 10 10 ns write recovery time twhax twr 0 0 0 0 0 ns tehax twr 0 0 0 0 0 ns data hold time twhdx tdh 3 3 3 3 3 ns tehdx tdh 3 3 3 3 3 ns write to output in high z (1) twlqz twhz 0 5 0 6 0 9 0 9 0 9 ns data to write time tdvwh tdw 5 6 7 8 8 ns tdveh tdw 5 6 7 8 8 ns output active from end of write (1) twhqx twlz 3 3 3 3 3 ns
5 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com edi8f32256c aug. 2001 rev. 13 eco #14561 write cycle 1 - w controlled write cycle 2 - e controlled fig. 4 fig. 5 e a tavav telwh tavwh twlwh tavwl twhax w high z data valid twlqz twhqx tdvwh twhdx q d a tavel high z tavav teleh e taveh tehax w twleh tehdx tdveh q data valid d
6 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com edi8f32256c aug. 2001 rev. 13 eco #14561 package description package no. 32: 64 lead angled simm note: 1. for gold simm change form edi8f to edi8g. ordering information part number speed package (ns) no. edi8f32256c12mnc 12 32 edi8f32256c15mnc 15 32 edi8f32256c20mnc 20 32 edi8f32256c25mnc 25 32 edi8f32256c12mmc 12 333 edi8f32256c15mmc 15 333 edi8f32256c20mmc 20 333 edi8f32256c25mmc 25 333 edi8f32256c12mzc 12 85 EDI8F32256C15MZC 15 85 edi8f32256c20mzc 20 85 edi8f32256c25mzc 25 85
7 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com edi8f32256c aug. 2001 rev. 13 eco #14561 package no. 333: 64 lead simm package no. 85: 64 pin zip all dimensions are in inches not recommended for new designs
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